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data sheet 1:2, differential-to-lvcmos/lvttl zero delay clock generator 87002-02 87002-02 rev c 7/13/15 1 ?2015 integrated device technology, inc. general description the 87002-02 is a highly versatile 1:2 differential-to- lvcmos/lvttl clock generator. the 87002-02 has a differential clock input. the clk, nclk pair can accept most standard differential input levels. internal bias on the nclk input allows the clk input to accept lvcmos/lvttl. the 87002-02 has a fully integrated pll and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625mhz to 250mhz. the reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency rati os: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the pll_sel pin can be used to bypass the pll for syst em test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the internal output dividers. features ? two lvcmos/lvttl outputs, 7 ? typical output impedance ? clk, nclk pair can accept the following differential input levels: lvpecl, lvds, hstl, hcsl, sstl ? internal bias on nclk to support lvcmos/lvttl levels on clk input ? output frequency range: 15.625mhz to 250mhz ? input frequency range: 15.625mhz to 250mhz ? vco range: 250mhz to 500mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 ? fully integrated pll ? cycle-to-cycle jitter: 45ps (maximum) ? output skew: 35ps (maximum) ? static phase offset: -10ps 150ps (3.3v 5%) ? full 3.3v or 2.5v operating supply ? 5v tolerant inputs ? 0c to 70c ambient operating temperature ? available in lead-free (rohs 6) package ? industrial temperature information available upon request 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 clk v dd sel3 sel2 sel1 sel0 v ddo q0 gnd nclk v ddo q1 gnd v ddo nc mr fb_in pll_sel v dda gnd 87002-02 20-lead tssop 6.50mm x 4.40mm x 0.925mm package body g package top view block diagram 0 1 q0 q1 pll_sel fb_in sel0 sel1 sel2 sel3 mr clk nclk pll 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 2, 4, 8, 16 32, 64, 128 pullup/pulldown pulldown pulldown pulldown pullup pulldown pulldown pulldown pulldown pin assignment
1:2, differential-to-lvcmos/lvttl zero delay clock generator 2 rev c 7/13/15 87002-02 data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 11, 18 gnd power power supply ground. 2, 19 q0, q1 output single-ended clock outputs. 7 ? typical output impedance. lvcmos/lvttl interface levels. 3, 17, 20 v ddo power output supply pins. 4, 5, 6, 7 sel0, sel1, sel2, sel3 input pulldown determines output divider values in table 3. lvcmos / lvttl interface levels. 8v dd power core supply pin. 9 clk input pulldown non-inverting differential clock input. 10 nclk input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 12 v dda power analog supply pin. 13 pll_sel input pullup pll select. selects between the pll and reference clock as the input to the dividers. when low, selects reference clock (pll bypass). when high, selects pll (pll enabled). lvcmos/lvttl interface levels. 14 fb_in input pulldown feedback input to phase detector for regenerating clocks with ?zero delay.? connect to one of the outputs. lvcmos/lvttl interface levels. 15 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the outputs to go low. when logic low, the internal dividers and the outputs are enabled. lvcmos / lvttl interface levels. 16 nc unused no connect. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output) v dd , v dda , v ddo = 3.465v 23 pf v dd , v dda , v ddo = 2.625v 17 pf r out output impedance 5 7 12 ?
1:2, differential-to-lvcmos/lvttl zero delay clock generator 3 rev c 7/13/15 87002-02 data sheet function tables table 3a. pll enable function table inputs outputs pll_sel = 1 pll enable mode sel3 sel2 sel1 sel0 reference frequency range (mhz) q0, q1 0000 125 - 250 1 0001 62.5 - 125 1 0010 31.25 - 62.5 1 0011 15.625 - 31.25 1 0100 125 - 250 2 0101 62.5 - 125 2 0110 31.25 - 62.5 2 0111 125 - 250 4 1000 62.5 - 125 4 1001 125 - 250 8 1010 62.5 - 125 x2 1011 31.25 - 62.5 x2 1100 15.625 - 31.25 x2 1101 31.25 - 62.5 x4 1110 15.625 - 31.25 x4 1111 15.625 - 31.25 x8
rev c 7/13/15 4 1:2, differential-to- lvcmos/lvttl zero delay clock generator 87002-02 data sheet table 3b. pll bypass function table inputs outputs pll_sel = 0 pll bypass mode sel3 sel2 sel1 sel0 q0, q1 0000 8 0001 8 0010 8 0011 16 0100 16 0101 16 0110 32 0111 32 1000 64 1001 128 1010 4 1011 4 1100 8 1101 2 1110 4 1111 2
1:2, differential-to-lvcmos/lvttl zero delay clock generator 5 rev c 7/13/15 87002-02 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = 0c to 70c table 4b. power supply dc characteristics, v dd = v dda = v ddo = 2.5v 5%, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ? ja 73.2 ? c/w (0 lfpm) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current 100 ma i dda analog supply current 16 ma i ddo output supply current 6ma symbol parameter test conditio ns minimum typical maximum units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current 96 ma i dda analog supply current 15 ma i ddo output supply current 6ma
rev c 7/13/15 6 1:2, differential-to- lvcmos/lvttl zero delay clock generator 87002-02 data sheet table 4c. lvcmos/lvttl dc characteristics, v dd = v dda = v ddo = 3.3v 5% or 2.5v 5%, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. in the parameter measurem ent information section, see output load test circuit diagrams. table 4d. differential dc characteristics, v dd = v dda = v ddo = 3.3v 5% or 2.5v 5%, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.3v 2 v dd + 0.3 v v dd = 2.5v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v -0.3 0.8 v v dd = 2.5v -0.3 0.7 v i ih input high current fb_in, sel[0:3], mr v dd = v in = 3.465v or 2.625v 150 a pll_sel v dd = v in = 3.465v or 2.625v 5 a i il input low current fb_in, sel[0:3], mr v dd = 3.465v or 2.625v, v in = 0v -5 a pll_sel v dd = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage; note 1 v ddo = 3.465v 2.6 v v ddo = 2.625v 1.8 v v ol output low voltage; note 1 v ddo = 3.465v or 2.625v 0.5 v symbol parameter test conditions minimum typical maximum units i ih input high current clk v dd = v in = 3.465v or 2.625v 150 a nclk v dd = v in = 3.465v or 2.625v 150 a i il input low current clk v dd = 3.465v or 2.625v, v in = 0v -5 a nclk v dd = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
1:2, differential-to-lvcmos/lvttl zero delay clock generator 7 rev c 7/13/15 87002-02 data sheet ac electrical characteristics table 5a. ac characteristics, v dd = v dda = v ddo = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to the output at v ddo /2. note 2: defined as the time difference between the input refere nce clock and the average feedback input signal, when the pll is locked and the input reference frequency is stable. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: this parameter is defined in accordance with jedec standard 65. table 5b. ac characteristics, v dd = v dda = v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossing point to the output at v ddo /2. note 2: defined as the time difference between the input refere nce clock and the average feedback input signal, when the pll is locked and the input reference frequency is stable. note 3: defined as skew between outputs at the same su pply voltage and with equal load conditions. measured at v ddo /2. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter test conditio ns minimum typical maximum units f max output frequency 15.625 250 mhz t pd propagation delay; note 1 pll_sel = 0v, f ? 250mhz, qx 2 4.8 5.8 ns t (?) static phase offset; note 2, 4 pll_sel = 3.3v, f ref ? 167mhz, qx 1 -160 -10 140 ps t sk(o) output skew; note 3, 4 pll_sel = 0v 40 ps t jit(cc) cycle-to-cycle jitter; note 4 f out > 40mhz 45 ps t l pll lock time 1ms t r / t f output rise/fall time 20% to 80% 400 800 ps odc output duty cycle 40 60 % symbol parameter test conditio ns minimum typical maximum units f max output frequency 15.625 250 mhz t pd propagation delay; note 1 pll_sel = 0v, f ? 250mhz, qx 2 4.9 6.7 ns t (?) static phase offset; note 2, 4 pll_sel = 2.5v, f ref ? 167mhz, qx 1 -240 -65 110 ps t sk(o) output skew; note 3, 4 pll_sel = 0v 35 ps t jit(cc) cycle-to-cycle jitter; note 4 f out > 40mhz 45 ps t l pll lock time 1ms t r / t f output rise/fall time 20% to 80% 400 700 ps odc output duty cycle 44 56 %
rev c 7/13/15 8 1:2, differential-to- lvcmos/lvttl zero delay clock generator 87002-02 data sheet parameter measureme nt information 3.3v output load ac test circuit differential input level cycle-to-cycle jitter 2.5v output load ac test circuit output skew static phase offset scope qx gnd v dda, v ddo v dd, 1.65v5% -1.65v5% nclk clk v dd gnd v cmr cross points v pp q0, q1 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles scope qx gnd 1.25v5% -1.25v5% v dd, v dda, v ddo qx qy t sk(o) v ddo 2 v ddo 2 nclk clk fb_in ? ? t (?) v oh v ol v oh v ol v ddo 2 t (?) mean = static phase offset where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on the controlled edges.
1:2, differential-to-lvcmos/lvttl zero delay clock generator 9 rev c 7/13/15 87002-02 data sheet parameter measurement in formation, continued output rise/fall time propagation delay output duty cycle/pulse width/period 20% 80% 80% 20% t r t f q0, q1 t period t pw t period odc = v ddo 2 x 100% t pw q0, q1 t pd v ddo 2 nclk clk q0, q1
rev c 7/13/15 10 1:2, differential-to-lvcmos/lvttl zero delay clock generator 87002-02 data sheet applications information power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is required. the 87002-02 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd, v dda and v ddo should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 ? resistor along with a 10 ? f bypass capacitor be connected to the v dda pin. the 10 ? resistor can also be replaced by a ferrite bead. figure 1. power supply filtering wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels v dd v dda 3.3v or 2.5v 10 10f .01f .01f
1:2, differential-to-lvcmos/lvttl zero delay clock generator 11 rev c 7/13/15 87002-02 data sheet differential clock input interface the clk /nclk accepts lvds, l vpecl, lvhstl, sstl, hcsl and other differential signals. both di fferential signals must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of th e driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. clk/nclk input driven by an idt open emitter lvhstl driver figure 3c. clk/nclk input driven by a 3.3v lvpecl driver figure 3e. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver figure 3f. clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t clk nclk differential input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
rev c 7/13/15 12 1:2, differential-to-lvcmos/lvttl zero delay clock generator 87002-02 data sheet schematic example figure 4 shows an example of 87002-02 application schematic. in this example, the device is operated at v dd = 3.3v. the decoupling capacitors should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver. figure 4. 87002-02 schematic example recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached.
1:2, differential-to-lvcmos/lvttl zero delay clock generator 13 rev c 7/13/15 87002-02 data sheet reliability information table 6. ? ja vs. air flow table for a 20 lead tssop transistor count the transistor count for 87002-02 is: 2578 package outline and package dimensions package outline - g suffix for 20 lead tssop table 7. package dimensions reference document: jedec publication 95, mo-153 ? ja vs. air flow linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 114.5c/w 98.0c/w 88.0c/w multi-layer pcb, jedec standard test boards 73.2c/w 66.6c/w 63.5c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. all dimensions in millimeters symbol minimum maximum n 20 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 6.40 6.60 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
rev c 7/13/15 14 1:2, differential-to-lvcmos/lvttl zero delay clock generator 87002-02 data sheet ordering information table 8. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-f ree configuration and are rohs compliant. part/order number marking package shipping packaging temperature 87002ag-02lf ics87002a02l ?lead-free? 20 lead tssop tube 0 ? c to 70 ? c 87002ag-02lft ics87002a02l ?lead-free? 20 lead tssop tape & reel 0 ? c to 70 ? c
1:2, differential-to-lvcmos/lvttl zero delay clock generator 15 rev c 7/13/15 87002-02 data sheet revision history sheet rev table page description of change date b t2 t8 2 10 11 12 14 pin characteristics table - added c pd specs. added recommendations for unused input and output pins section. updated differential clock input interface section. added schematic layout ordering information table - added lead-free marking. 4/29/08 c t5a, t5b t5b t8 7 7 10 14 added thermal note. 2.5v ac characteristics table - due to datas heet conversion on april 29, 2008, corrected typo for static phase offset spec from -650 to -65. updated wiring the differential levels to accept single-ended levels section. ordering information table - deleted ?ics? pr efix from the part/order number column. updated header/footer of datasheet. 8/9/10 c t8 14 ordering information - removed leaded devices. updated data sheet format. 7/13/15
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